IPSH6N03LA G

OptiMOS®2 Power-Transistor IPDH6N03LA G IPFH6N03LA G IPSH6N03LA G IPUH6N03LA G Product Summary Features • Ideal for high-frequency dc/dc converters • Qualified according to JEDEC1) for target application V DS 25 V R DS(on),max (SMD version) 6 mΩ ID 50 A • N-channel, logic level • Excellent gate charge x R DS(on) product (FOM) • Superior thermal resistance • 175 °C operating temperature • Pb-free lead plating; RoHS compliant Type IPDH6N03LA G IPFH6N03LA G IPSH6N03LA G IPUH6N03LA G Package PG-TO252-3-11 PG-TO252-3-23 PG-TO251-3-11 PG-TO251-3-1 Marking H6N03LA H6N03LA H6N03LA H6N03LA Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID Value T C=25 °C2) 50 T C=100 °C 50 Pulsed drain current I D,pulse T C=25 °C3) 350 Avalanche energy, single pulse E AS I D=50 A, R GS=25 Ω 150 Reverse diode dv /dt dv /dt I D=50 A, V DS=20 V, di /dt =200 A/µs, T j,max=175 °C 6 Gate source voltage4) V GS Power dissipation P tot Operating and storage temperature T j, T stg T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 1.5 Unit A mJ kV/µs ±20 V 71 W -55 ... 175 °C 55/175/56 page 1 2008-04-14 Parameter IPDH6N03LA G IPFH6N03LA G IPSH6N03LA G IPUH6N03LA G Values Symbol Conditions Unit min. typ. max. - - 2.1 minimal footprint - - 75 6 cm2 cooling area5) - - 50 25 - - Thermal characteristics Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA Gate threshold voltage V GS(th) V DS=V GS, I D=30 µA 1.2 1.6 2 Zero gate voltage drain current I DSS V DS=25 V, V GS=0 V, T j=25 °C - 0.1 1 V DS=25 V, V GS=0 V, T j=125 °C - 10 100 V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=30 A - 8.2 10.2 mΩ V GS=4.5 V, I D=30 A, IPD version - 8 10 V GS=10 V, I D=50 A - 5.2 6.2 V GS=10 V, I D=50 A, IPD version - 5 6 - 1.3 - Ω 35 69 - S Gate resistance RG Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=50 A 1) J-STD20 and JESD22 2) Current is limited by bondwire; with an R thJC=2.1 K/W the chip is able to carry 80 A. 3) See figure 3 4) T j,max=150 °C and duty cycle D